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Honored ContributorGXB:tranceiver transmission time issue
Hi dears: I have a board which has two same FPGA. Each FPGA has one transmitter. These two FPGA are configured with same configuration file. I use aonther board which has only one FPGA to recei...
Altera_ForumHonored Contributor
Honored ContributorHi Jerry,
You need to investigate your data transport in a little more detail. You also need to document those tests. Here's an example for an ADC I am testing; http://www.ovro.caltech.edu/~dwh/wbsddc/hittite_adc_hw.pdf In this case, I had no choice but to use a PRBS generator for lane-to-lane synchronization. In your case you can use 8/10B encoding and create logic to align lanes. You need to focus on getting your data transport between multiple FPGAs synchronous, and aligning their pipeline delays after power-on reset. Create a Modelsim simulation with two FPGAs, multiple transceiver signals, delay the transceiver signals by different amounts (more than a few bit periods), and then try to resynchronize, i.e., align the parallel output words, in the receiver FPGA. Cheers, Dave
