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Ok.
So what protocol are you using? Since you control the transmit and receive, you get to define what gets used.
Where does this signal come from, and how do you ensure your ADCs all use a common clock reference? Is the pulse synchronous to the ADC clock reference?
These timestamps should be system-level synchronous, and synchronous to the master clock.
For example, in my systems we use GPS units with a 1pps output and 10MHz reference. The 10MHz reference is then the synthesizer reference for several hundred 1GHz ADCs.
You have not explained how anything is synchronous or synchronized yet.
This can be made to work.
Whether or not the receiver channel offsets stay the same depends on how you clock your transceivers. If you use a global clock signal, then both the transmitter and receiver will have the same frequency, and the offsets will not change with time after power-on. This means you can power-up your system, send a test pattern through the network, determine offsets, delete bytes until the transmit-to-receive links all have the same delays, and then "go".
If however you are using independent oscillators on each of your boards, then some oscillators will be slightly faster or slower than others, and eventually your receive FIFOs will over- or under-flow. There are protocols that can deal with this, which they do by inserting or removing 10-bit stuff codes. Your system should not be using these types of protocols.
Cheers,
Dave
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Hi Dave:
1. I selected basic mode in MegaWizard when i implement GXB megacore. So we don't use any standard protocol for we only send data from point-to-point.
2. Each channel process one analog signal. Which is divided into two parts on another FEE board. One part is used to generate ADC input signal, another is used to generate TDC input signal(trigger signal, just filter the analog signal's leading edge). So if two channels have events happening at the same time, they should have same timestamp. And they should arrive at StratixIVGX board at the same time in real. But, there may have some non-pipeline process which cause these two evnets can't arrive at StratixIVGX at the same. We must take care of these non-pipeline issues (such as the offset of different GXB).
3. Except FEE board, all digitized boards use same oscillator source from backplane board. It means all ArriaGX baords and StratixIVGX board are plugged on single backplane board. The hardware clock tree have has several clock distributor chips on backplane and each sub-board.
3
Thanks
Jerry
Honored Contributor
