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The same issue occurs if you use one chip. For example, lets say you have an HSMC connector adapter which loops back the Gbps transmitters and receivers. If you took a common signal, eg., a PRBS7 sequence, and sent it to all 8 transmitters, then looked at the output of all 8 receivers, they will all be different, with an arbitrary offset at the single-bit level. You can configure the ALTGX block in the Stratix IV series devices to synchronize to a start pattern.
If you perform a test between two boards, then you can add another complication; different transmitter reference clocks.
PCIe x4 "works" because the transceiver interface defines 10bit codes for "channel bonding". If you are creating a custom Gbps link then you can use the same technique.
The appropriate solution depends on what you are trying to do. Until you explain that, its a bit difficult to provide suggestions.
You're looking at data in the parallel clock domain of the FPGA. There are many layers of FIFOs and clock-domain crossing logic, with many opportunities to lose clocks when looking at multiple transceiver channels.
Cheers,
Dave
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Hi Dave:
My project, one board using two FPGA (ArriaGX) processing "pulse" events, which have ramdom timestamp. Another board using single FPGA (Stratix IVGX) receive the processed data and sort those events according timestamp.
Given a GXB channel, if each event transmission with ramdom offset, it's difficult for StratixIV to sort those events. If the offset is a constant value after power-on, it seems i could make padding to compensate this transmission offset in different lanes. But, as you said, different lanes should have arbirary offset. Also according my first post JPG shows, it should be ramdom offset. I really don't know how to align them?
Please give me some guidelines. Thanks in advance!
Jerry
Honored Contributor
