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1. Do you mean this issue basicly because of these two lanes are in different chips? Otherwise, how can we implement pcie-x4 in single chip, am i right?
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The same issue occurs if you use one chip. For example, lets say you have an HSMC connector adapter which loops back the Gbps transmitters and receivers. If you took a common signal, eg., a PRBS7 sequence, and sent it to all 8 transmitters, then looked at the output of all 8 receivers, they will all be different, with an arbitrary offset at the single-bit level. You can configure the ALTGX block in the Stratix IV series devices to synchronize to a start pattern.
If you perform a test between two boards, then you can add another complication; different transmitter reference clocks.
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Otherwise, how can we implement pcie-x4 in single chip, am i right?
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PCIe x4 "works" because the transceiver interface defines 10bit codes for "channel bonding". If you are creating a custom Gbps link then you can use the same technique.
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2. I am trying to understand your "solution". I use basic mode, but i enable 8b/10b in megawizard. Is it possible for me to solve this issue without changing current
gxb settings? If this is the case, can you point it to me which is of the "frame synchronization controls"? I don't use any 8b/10b control signals in my previous designs.
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The appropriate solution depends on what you are trying to do. Until you explain that, its a bit difficult to provide suggestions.
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3. Why they are diffrent so big, with Max difference of about 10 parallel clcok cycles(for my system it's about 100 ns , 10 100Mhz cycles)? Assume my logic process parallel data with pipelining, there is no difference process timing.
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You're looking at data in the parallel clock domain of the FPGA. There are many layers of FIFOs and clock-domain crossing logic, with many opportunities to lose clocks when looking at multiple transceiver channels.
Cheers,
Dave
Honored Contributor
