Honored Contributor
Honored ContributorThis is "normal" for GXB signals.
GXB transmitters and receivers serialize and deserialize data. The problem with these shift-registers is that you cannot really start or stop them synchronously at both the source and destination, since they're in different chips, and the bit-streams are at Gbps data rates. The "solution" to get around this lack of synchronization is to introduce a protocol for the data sent over the link. For example, send a known pattern over the link, and align each of the receivers to output parallel words based on that pattern - pseudo-random binary sequences are one method of doing this. Protocols like Gigabit Ethernet use 8/10B and 64/66B encoding and they use special lane synchronizing characters, so that you can align the 8-bit output data on one lane, and they use channel bonding characters so that you can align the data across multiple lanes. If you control both ends of the serial link, then the easiest solution is to use 8/10B encoding, and then use the frame synchronization controls provided by Altera's IP cores. Cheers, Dave
