New Contributor
Regular ContributorHi Lorenzo,
"In CycloneIV Handbook Table 7-2 shows Device DQS and DQ Bus Mode Support; my memory is x32. It's possible to connect x32 DDR2 to EP4CE6 using two x16 Groups, Bottom and Top?"
Regards,
Adzim
New ContributorThank you for your response. I still have a few more questions.
The actual FPGA is Cyclone III and the memory a PSRAM. The new version must drive a double LVDS display (1920x720). Cyclone III is no longer supported and Cyclone III and IV were removed from "External Memory Interface Handbook" in 2013. For this reason i chose Cyclone V E (i don't need ..), F484 or U484.
My questions:
1) Is it possible to control one DDR2 x32 chip using 2 Top x8 groups and 2 Bottom x8 groups?
2) My DDR2 run at 200 MHz, it is fair to say that it is enough to use 4 x8 groups and Soft Memory Controller, so can i use 4 x8 Bottom groups of a Cyclone V E A2 UBGA484 or FBGA484 or MBGA383?
3) Apart from speed, are there any other parameters that differentiate Soft Memory Controller from Hard Memory Controller?
4) Is there an example of an application of a DDR2 memory controller without the NIOS?
Grazie per ogni risposta.
