Forum Discussion
Altera_Forum
Honored Contributor
14 years agois this for ADAT or TOSLINK? looks like fun
ideally you would do simulations on your I/O using IBIS models and HyperLynx or compatible software. you stick in a model of the FPGA I/O, a model of the trace, and the far side I/O model. you can then tweak the drive strength, slew rate, and termination resistors to optimize the signal integrity on the other hand that may be overkill for a senior project