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Altera_Forum
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Honored ContributorGot Confdone signal but ist not working right
Hi, i'm news to this forum and already have a problem. (Most of the user joined this forum this way i guess).
I'm using - Cyclone 3 EP3C10F256C8 - Quartus 2 V8.0 - Byteblaster 2 I whant to run a simple test program to start. If i mean simple, i mean:beginclk0 <= '0'; clk1 <= '0'; clk2 <= '0'; clk3 <= '0'; clk4 <= '0'; end; [/INDENT]Everything seems alright, quartus 2 gives warnigs but not extrodinary. The programmer (JTAG) detects 2 devices EP3C10/5 UNKNOWN_792603F The second device is a processor (i know cause its the same numbers) The first is the FPGA the device. Now the device he detects is not the same as EP3C10F256C8, is it? Quartus gives programming succesfull and CONF_DONE pin goes HIGH but the INIT_DONE stays low. What can be the problem? Thanks anyway for the responds that will follow.10 Replies
Altera_ForumI realised now i forgot the pull_up for init_done pin. Srry but i overlooked in the scematics. Thx for the help.
- Altera_Forum
Weird i remade the project and it is working right now...
Srry but i can't help to find a solution for this problem. Thx for helping me anyway! - Altera_Forum
No time for today. Working till 5 but.
Init_Done remains low and a device is working. I just send the input CLK to a pin but inverted en one pin low (cause normally they r HIGH). And that is working. But the INIT_DONE pin remains Low. If i load a other design ... All pins are high except INIT_DONE. Maybe it is a setting? One that i did change in this project. - Altera_Forum
There can be conf done timing issues, raise the issue through my support. Attach scope plots of CONF_DONE
- Altera_Forum
Conf_done is connected with 10K to 3.3V
(Before this is was connecter with 10 K to 3.3 and with 1 k to a transistor for driving a LED. But this is removed cauze i thaugt it would change something No result.) If u know where to upload images is can give you one. - Altera_Forum
Hi,
What else do you have connected to CONF_DONE with full details? Thanks - Altera_Forum
New update:
I scratched some layers so only one device is on the chain. Its still the same. Conf_Done lights up (LED) Init_Done stays low. When I don't use Init_Done pin (in settings) it works like all the other outputs, who are High. - Altera_Forum
So i have 2 devices on the Chain. And the FPGA is first.
Because i only configure the FPGA (first place) and not the ARM processor is it possible that JTAG doesn't let the FPGA start in user mode? How can you bypass the processor with the Quartus II programmer? I was used to a Xillinx enviroment. I'm pretty new at this. - Altera_Forum--- Quote Start --- It is the same. C5 and C10 have identical IDs. --- Quote End --- Ok Thx --- Quote Start --- Did you enable the pin in device configuration, did you connect a pull-up resistor? --- Quote End --- Yes and Yes Thx for quick reply
- Altera_Forum--- Quote Start --- Now the device he detects is not the same as EP3C10F256C8 --- Quote End --- It is the same. C5 and C10 have identical IDs. --- Quote Start --- but the INIT_DONE stays low --- Quote End --- Did you enable the pin in device configuration, did you connect a pull-up resistor?
