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Altera_Forum's avatar
Altera_Forum
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15 years ago

Global Clock vs. Input

Hey Guys,

as you probably know, I am the dude with the easy questions. For me programming my first CPLD plenty of things are new and unclear to me.

As my CPLD-Design is done and hopefully works, I am about to assign the input and output pins to my CPLD using Pin Planner. I came across a pin called Global Clock. I have understood, that this pin can be used for normal I/O pins as well as "providing clock for all resources within the device including LE's, Lab local interconnect, I/0 elements and the ufm block."

I have read too, that I need to assign the input pin to assignment name "global signal" and the value "global clock".

This leads to my actual question. In my CPLD-Design I have used a clock signal to drive all Flip-Flops, counters, etc. The signal to the input pin is delivered by a quarz oscillator (40 Mhz). I wonder, if I should declare my clock input pin as "global clock", as the clock signal does not have any relationship with other inputs except in the FF synchronisation chain at the entry of the inputs into the CPLD program.

Could/should I declare my clock signal as global clock? I would like to understand the exact difference between declaring a clock signal as global clock and leaving the clock signal as a usual input.

Every answer is appreciated!

Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    As I understand it, signals declared as a global clocks are routed on a special dedicated path (there is a limited number of these) designed in the device that fans out to all the logic cells, rather than having to pass through any routing configuration mux-gates to get the signal to the various cells that use it. This reduces the latency of this signal to related synchronous logic, and possibly increasing Fmax.