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Altera_Forum's avatar
Altera_Forum
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12 years ago

Giving external input to Triple Speed Ethernet

Hello everybody,

I want to modify the tutorial "using Triple Speed Ethernet" according to my requirement. In brief what I used is: Qsys(Hardware Generation), NIOS II Eclipse(ApplicationSoftware: C/C++), Wireshark(to see the output in PC coming through Ethernet Interface) and Networking (Ctr+shift+Alt: to see the Link Speed, which is 770 Mbps).

Input is defined within application C/C++ Program in NIOS II Eclipse software as transmitted frame.

I would like to know if I have to give continuous data stream from some pins of FPGA (or after some processing in FPGA) as input to ethernet, what should I do?

I see Conduit Connection in used tse_mac IP core of Qsys. I also see conduit connection in top level generated verilog code. should I modify the generated verilog code in this top level entity to give input and again compile the program or is there any other method?

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Regards

FPGA beginner

25 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Yes, you can definitely do it that way (export and manually connect the signals). But my preference is to follow the approach in the UDP offload example, and bundle your IP in Qsys components in order to avoid having to make those connections manually, and to make it easier to build a more complex system in the future.

    And yes, you always have to recompile the project if you change something.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Hi, I didn't get the point: send and receive packets through the software API. which API software can be used in this case?

    --- Quote End ---

    It depends on what you choose to usr as a software platform. The Altera examples use the uCOS II embedded operating system with the Interniche TCP/IP stack. This has a standard bsd sockets api (https://en.wikipedia.org/wiki/bsd_socket) that you can use to send packets from the software. Other developers prefer to use LwIP or Linux.

    But you will never be able to generate 750Mb+ traffic with a software solution. You need to generate your packets in hardware, and the offload example indicated by ted is a good starting point.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    If I remove this SGDMAs, where exactly I have to connect (to the avalon stream interfaces) from own IP.

    --- Quote End ---

    You would connect to the "transmit" and "receive" Avalon Streaming ports of the TSE MAC.

    See this page:

    http://www.alterawiki.com/wiki/nios_ii_udp_offload_example

    In that example, IP blocks are connected in addition to the SGDMA (through the packet multiplexer/demultiplexer pair).

    Replace the "PRBS packet generator", "UDP payload inserter", and "Alignment pad inserter" with your own IP (and same thing on the receive side, if needed).

    If you don't need the NIOS / SGDMA, then you probably delete the multiplexer/demultiplexer as well and connect directly to the TSE MAC.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Usually in a design with a Nios II CPU and a software layer with a TCP/IP stack, those two interfaces are connected to SGDMAs in QSys. If you do it that way and have the correct software solution, then you can directly send and receive packets through the software API.

    --- Quote End ---

    Hi, I didn't get the point: send and receive packets through the software API. which API software can be used in this case?

    --- Quote Start ---

    If you need a higher bandwidth you can also make your own IP and connect it to the avalon stream interfaces in QSys instead of the DMAs and generate packets directly there.

    --- Quote End ---

    yes, I need higher bandwidth 750 Mbps+. In attachment, there is screenshot of how I connect SGDMAs to other components in Qsys. If I remove this SGDMAs, where exactly I have to connect (to the avalon stream interfaces) from own IP.
  • Altera_Forum's avatar
    Altera_Forum
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    The TSE uses two Avalon Stream interfaces for Ethernet packets: a source with received packets and a sink for packets to transmit. Usually in a design with a Nios II CPU and a software layer with a TCP/IP stack, those two interfaces are connected to SGDMAs in QSys. If you do it that way and have the correct software solution, then you can directly send and receive packets through the software API.

    If you need a higher bandwidth you can also make your own IP and connect it to the avalon stream interfaces in QSys instead of the DMAs and generate packets directly there.