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Altera_Forum
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9 years ago

Getting rid of some differential I/O pins and PowerPlay warnings

Hello, I am programming a MAX10 FPGA on Quartus Prime and I got the following warnings: Critical Warning (16562): Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I don't see an advantage of specify separate positive and negative pins in HDL although it's actually a single differential signal that must use dedicated pin pairs.

After the (n) pins have been automatically supplemented in pin planner, they should have regular pin assignments and don't give a warning.