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Altera_Forum's avatar
Altera_Forum
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9 years ago

Getting rid of some differential I/O pins and PowerPlay warnings

Hello, I am programming a MAX10 FPGA on Quartus Prime and I got the following warnings: Critical Warning (16562): Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I don't understand. If you're not using differential signaling, why are you using a differential I/O standard? Quartus is looking at the I/O standard you set for the signal on LVDS_in1 and LVDS_in2. If you don't mean to be using a differential I/O standard, change it to a single ended standard in the Pin Planner. Then it won't try to create an n pin for you that you're not even going to be using.