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Altera_Forum
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9 years ago

Getting rid of some differential I/O pins and PowerPlay warnings

Hello, I am programming a MAX10 FPGA on Quartus Prime and I got the following warnings: Critical Warning (16562): Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Just in case this might help to solve my problem, the critical warning has no further info messages (unfortunately) and the warning about the differential signals displays the following messages:

Warning (176118): Pin "LVDS_in1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LVDS_in1(n)"

Warning (176118): Pin "LVDS_in2" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LVDS_in2(n)"

As I cannot create a LVDS_in1(n) input as such (that would generate an error) I am still wondering how I could tell the tool I am using two differential LVDS signals... Is there any MAX10-compatible differential buffer?

Thanks!