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Honored Contributor
Honored ContributorGenerating a Sine Wave
Hello Friends, I am a newbie.. hope you dont mind if my query is odd.. i wanted to the know like how can we generate a SINE WAVE.. by writing a verilog or vhdl code. i browsed throug...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- First of all, you can not use system task (e.g. $readmemb) in synthesis, system tasks and functions are basically for verification/simulation. So if your intention is to simulate your design you can use system task and function. --- Quote End --- Afaik Xilinx ISE lets you do it (at least they let you use the VHDL equivalent), and is mentioned in one of its code templates for initialising memories. Its a real shame that Quartus wont support it.
