Generating a Sine Wave

First of all, you can not use system task (e.g. $readmemb) in synthesis, system tasks and functions are basically for verification/simulation. So if your intention is to simulate your design you can use system task and function.

You can use integer data type for your variable to let simulator know about negative numbers or add one more bit in at MSB to indicate sign of number (e.g. 1 at MSB represent negative value, 0 for positive). I think you should be able to load memory content using $readmemb from a text file. Make sure the format of text file is as mentioned in LRM of Verilog.

I would suggest you to look at some good verilog programming book or LRM to have more idea on programming.