Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Generating 250MHz clock from Arria V to ADC

Hi, We want to use Altera Arria V(5AGXMB1G4F35C5N) FPGA interfaced with TI ADC ADS6129IRGZ. We are deriving 250 MHz clock required for the ADC using the PLL (ALTPLL core) availale on the device an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

Thanks for your reply.

I checked for jitter specs, Device specification mentions of a max period jitter of 0.250 ns for Arria V fractional PLLs. Is it recommended to use this as clock for ADC for clock freq 250MHz?

ADC input is a Pulse with different level of amplitudes.

Thanks

Ashwini

--- Quote End ---

What about adc clock jitter requirement.

Moreover the adc data and clock to fpga may suffer similar jitter of .25 ns per 4 ns period, pretty tight on fpga timing. You will need to enter clock uncertainty to cover the .25 ns and see report of timing.