Generating 250MHz clock from Arria V to ADC

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Thanks for your reply.

I checked for jitter specs, Device specification mentions of a max period jitter of 0.250 ns for Arria V fractional PLLs. Is it recommended to use this as clock for ADC for clock freq 250MHz?

ADC input is a Pulse with different level of amplitudes.

Thanks

Ashwini

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What about adc clock jitter requirement.

Moreover the adc data and clock to fpga may suffer similar jitter of .25 ns per 4 ns period, pretty tight on fpga timing. You will need to enter clock uncertainty to cover the .25 ns and see report of timing.