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Altera_Forum
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10 years ago

Generating 250MHz clock from Arria V to ADC

Hi, We want to use Altera Arria V(5AGXMB1G4F35C5N) FPGA interfaced with TI ADC ADS6129IRGZ. We are deriving 250 MHz clock required for the ADC using the PLL (ALTPLL core) availale on the device an...
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Altera_Forum
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10 years ago

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Yes, I believe kaz is correct. Check the worst case jitter specification for a dedicated PLL output and you'll find it's in the neighborhood of 10% of UI.

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Thanks for your reply.

I checked for jitter specs, Device specification mentions of a max period jitter of 0.250 ns for Arria V fractional PLLs. Is it recommended to use this as clock for ADC for clock freq 250MHz?

ADC input is a Pulse with different level of amplitudes.

Thanks

Ashwini