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Honored Contributor
Honored ContributorGenerating 250MHz clock from Arria V to ADC
Hi, We want to use Altera Arria V(5AGXMB1G4F35C5N) FPGA interfaced with TI ADC ADS6129IRGZ. We are deriving 250 MHz clock required for the ADC using the PLL (ALTPLL core) availale on the device an...
Altera_ForumHonored Contributor
Honored ContributorYes, I believe kaz is correct. Check the worst case jitter specification for a dedicated PLL output and you'll find it's in the neighborhood of 10% of UI.
