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Hi,
We want to use Altera Arria V(5AGXMB1G4F35C5N) FPGA interfaced with TI ADC ADS6129IRGZ. We are deriving 250 MHz clock required for the ADC using the PLL (ALTPLL core) availale on the device and clock output is sent on the differential clock lines. We have used the output clock as a regional clock (ALTCLKCTRL). Are there any limitations wrt to the clocking scheme described? Is the clocking network described gives proper optimum output skew and SNR?
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as far as I know fpga generated external clocks suffer high jitter and may not be good for ADC clocking. I would rather use a clean external oscillator. check the spec of your ADC clock and fpga jitter figures.
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