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Altera_Forum's avatar
Altera_Forum
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15 years ago

generate problem

Hi friends, I try to replicate a module by N (parameter) times. Each small instance is connected (wire) with prev and next. In original design (fixed 8 cells) I just declared 8 wires wire ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you very much FvM, it worked nice. A small problem now

Critical Warning (10846): Verilog HDL Instantiation warning at shifterNmsb.v(45): instance has no name

wire w[N:0]; // N+1 wires

generate

for ( i = 0; i <= N-1; i = i+1 )

begin: inst

shiftcell (

.Load(Load),

.Clock(invSCK),

.Din(DataIn),

.prev(w),

.Dout(w[i+1])

);

end

endgenerate