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Altera_Forum's avatar
Altera_Forum
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15 years ago

generate problem

Hi friends, I try to replicate a module by N (parameter) times. Each small instance is connected (wire) with prev and next. In original design (fixed 8 cells) I just declared 8 wires wire ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Perhaps zuzu22 wants to say that he is constrained to use out7 from the external design.

He can generate the architecture using out[7] but he then needs a module that translate these signal inputs in out7.

It seems that he wants to "construct" the name of the signal using "i".

I don't know how to solve the problem, however.