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Altera_Forum
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14 years ago

Generate patterns through CPLD(MAXII)?

I'm new to FPGA/CPLD. Could any one help me? I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. For example, under 50MHz clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi Dave,

Sorry to let you wait.

I need to correct my statement.

1. My intention is to have simple test to microcontrollers (not specific one). For ex. Idd/power consumption, flash operation.

2. Some MCUs are not desgined with JTAG interface for test but they have similar serial interfaces (may be some specific protocols) that I have to deal with. Each one might be different.

3. As a result, I plan to use FPGA to generate patterns to access the chips. The patterns that I need to geneate would around be 2-10 pins. And there will be up to 10~30 types of patterns for each pin to enter test mode and setup control signals.

As a result, I need to make up my mind:

1. Which FPGA/CPLD would be suitable for me

2. How to generate patterns, simply through shift registers and input patterns from my laptop?

best regards,