Generate 10 phase clock for 10 ADC from Cyclone III - Is it possible?

Yes - indeed you can. However, the GCLK network is a set of low latency paths intended to clock the internal logic of your FPGA. Depending on the part you use you'll have 10 or 20 GCLK resources available to you. If you use these up simply routing PLL clock output phases (that aren't used inside the FPGA) to I/O pins, then you will run out of these resources quickly. Depending on how full your FPGA is this could cause Quartus difficulty in fitting your design and making it meet timing.

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Only the C0 output counter can feed the dedicated external clock outputs.

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This is a low latency path whose delay will differ from any other PLL output clock phases routed to I/O via GCLK. So, you may end up with a set of clock signals whose relative phases aren't quite what you want.

If you're careful - yes - this could all be made to work. However, if it were me, I'd use an external clock generator.

Cheers,

Alex