Generate 10 phase clock for 10 ADC from Cyclone III - Is it possible?

Use and external clock generator.

There are a serious issues in trying to use multiple outputs from a single PLL to drive circuitry outside the FPGA. Typically, only one of the PLL's output clocks is intended for routing to an external pin. The others are intended or use inside the FPGA and the routing resources in the FPGA are designed to support that.

If you start pushing multiple clocks from the PLL to pins the FPGA will use routing resources that that ae not ideally suited. This will introduce very varied delays meaning any phase relationship you specified at the output of he PLL will be compromised. Worse still, each time you route the FPGA these delays will change - unless you're able to lock down certain resources specifically, which will prove to be difficult.

Read through chapter 5 - "clock networks and plls in the cyclone iii device family (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii51006.pdf)" of the Cyclone III handbook. Table 5-3 and figure 5-6 show the Cyclone III PLL. One Dedicated clock output is the important bit here.

Cheers,

Alex