Generate 10 phase clock for 10 ADC from Cyclone III - Is it possible?

Forgive me for saying but if you are aware of a design that successfully does this - why ask the question?

MAX II devices do not have PLLs. So they will not be responsible for generating the clocks you mention. If the clocks are routed through the MAX II, having been generated elsewhere, then I'd question the resulting phase accuracy.

Cyclone III PLLs can only generate 5 output clocks. Whilst it will happily generate 5x 100MHz clocks, shifted +1ns each, you clearly need 2 PLLs to solve 10 clocks. Fine. However, you'll have great difficulty ensuring an accurate phase shift between the two PLLs. So, you'll end up with two sets of five clocks, accurate to each other but very likely to be shifted with respect to each other. This shift maybe small and possibly small enough to allow a solution.

Cyclone V PLLs support 9 output clocks. So, conceivably you could generate 10 phases, as you need, by using the source clock in addition to the 9 PLL output clocks. However, you will still have trouble accurately controlling the phase of the 9 output clocks with respect to the source.

The Stratix & Arria families offers PLLs with more (18) output clocks. If I was looking to solve this, I'd be looking to these families.

Cheers,

Alex