Gate Level Simulation with Modelsim

Hello,

I got a problem with gate level simulation with Altera Modelsim. I have properly compiled project files Test.vho and Test_vhd.sdo. I have additionaly written a testbench in vhdl. Now in order to simulate I'm choosing Start Simulation, klicking the testbench file and adding the .sdo file in SDF tab. Here i have a problem because i dont know what to type in the "Apply to Region" textbox. It shall be the instance name of the project (not testbench), but where shall i get it from ? I can't make it work.

Please help !

Regards

Joel