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Altera_Forum
Honored Contributor
13 years agoFTDI FT2232H Sync FIFO + FPGA
Hi guys,
I'm using Morph-IC II and i'm having problems establishing the usb-communication between my Cyclone 2 and the FTDI FT2232H. My objective is to send a start/reset signal from PC->FPGA, then access the data from the FPGA till an end/reset signal. My problem is now the combination of sending/receiving. I configured the FTDI in Synchronous FIFO Mode(getting the 60MHz clk) and it works fine when i send only in 1 direction. This task has not to be parallel,it should go like this: PC->START->FPGA switch to read FPGA->DATA->PC switch to write PC->STOP->FPGA (VHDL) To achieve this I have a state machine for sending and one for receiving. These 2 are working fine when i only use one and comment out the other... By the way,if I comment out only the line where i access the data it works also,but without data not very useful^^ I dont know exactly how i should switch between the write/read state machines...right now i react on RXF low,which indicates that the FTDI(PC) has data to send,because the PC sends only start/stop/reset-commands,i prefer these. On PC(C#) side I use the D2XX-drivers. Init the Module and use SetBitMode to go into Synchronous FIFO,then read/write with the FTDI-functions. I've read something about configuring the data-pins as in/output with the SetBitMode-Mask,but i didn't made progress using this. Has anyone of you done this before and can help me? Is it possible to serial read/write in this mode or only 1 direction possible? Any hints are welcome :), if you need more informations,code,... just say Thank you very much for help, Best Regards, Andreas15 Replies
- Altera_Forum
Honored Contributor
Hi Günther,
--- Quote Start --- since I'm planning to use exactly this setup, do you mind sharing your source? I really don't want to re-invent the wheel. --- Quote End --- Sure. How familiar are you with Qsys and IP cores? Do you have a top-level design for your FPGA project yet, eg., a top-level entity and a pin assignments script? If you do, sent it to me, and I'll create a dummy project with a Qsys system and the bridge included. That'll allow me to ensure that I've included all the correct files. Cheers, Dave - Altera_Forum
Honored Contributor
Hi Dave/Stylopath,
since I'm planning to use exactly this setup, do you mind sharing your source? I really don't want to re-invent the wheel. regards, Günther - Altera_Forum
Honored Contributor
Thank you,I will read through your document,hope I find help there
any other suggestions? --> Working now,thank you for help!!! - Altera_Forum
Honored Contributor
Hi Andreas,
Here's my notes on interfacing to these devices http://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi.pdf I plan on posting the code eventually, however, I'm still hacking away on it when I get time ... Cheers, Dave- hon1
New Contributor
Hi Dave,
I hope to learn from your notes on interfacing the FTDI chip but the link is not working. Possible for you to post your notes again?
Best,
Hon