FT2232H 245 Synchronous FIFO Mode problem

With great FTDI support I have solved problem TXE signal can go HIGH on falling edge of clock and so it must not be checked only on rising edge.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ft232h_tx is
   port 
   (      
      FT_CLK   : in std_logic;                     -- 60 MHz FT232H clock
      nTXE      : in std_logic;                     -- Can TX
      nRXF      : in std_logic;                     -- Can RX
      nRD      : out std_logic;                     -- Read
      nSIWU      : out std_logic;                     -- Send Immediate / WakeUp
      nOE      : out std_logic;                     -- Output enable
      nWR      : buffer std_logic;                  -- FIFO Buffer Write Enable
      ADBUS      : out std_logic_vector(7 downto 0)   -- Bidirectional FIFO data               
   );
end entity;
architecture rtl of ft232h_tx is
   signal counter : unsigned (7 downto 0) := "00000000";
   signal state : std_logic := '0';
begin
   
   -- don't read
   nOE <= '1';
   nSIWU <= '1';
   nRD <= '1';
   
   process(FT_CLK, nTXE)      
   begin   
      if (rising_edge(FT_CLK)) then
         if(nTXE = '0') then
            if(state = '1') then
               --nWR <= '0';
               ADBUS <= std_logic_vector(counter);
               counter <= counter + 1;
            end if;
            state <= '1';
         else
            --nWR <= '1';
            state <= '0';                     
         end if;
      end if;      
   end process;
   nWR <= '1' when nTXE = '1' else 
          '0' when (nTXE ='0' and state = '1');
   
end rtl;