FT2232H 245 Synchronous FIFO Mode problem

Hello

Its been a while seen i placed with this stuff hehe, I ended up going with a STM32F04 micro instead of the ftdi/fpga

Here is my code, hopefully if helps you out :)

I am sending data the opposite direction, from the pc to the fpga.

.c

FT_SetBitMode(ftHandle, 0xff, 0);
Sleep(10);
FT_SetBitMode(ftHandle, 0xff, 0x40);
FT_SetLatencyTimer(ftHandle, 16);
FT_SetUSBParameters(ftHandle,0x10000, 0x10000);
FT_SetFlowControl(ftHandle, FT_FLOW_RTS_CTS, 0x0, 0x0);
FT_Purge(ftHandle, FT_PURGE_RX);
Sleep(10);

fpga

// *****************************
// FT2232H Synchronous 245 FIFO
// *****************************
always @(posedge fifo_clk)
begin
    case(fifo_state)
        0:  begin // wait for rxf to go low (byte available)
                if(rxf==0)
                begin
                    oe=0;
                    fifo_cnt=0;
                    fifo_state=1;
                end
            end
        1: begin
                rd = 0;
                fifo_state=2;
            end
        2: begin
                // keep reading data untill rxf goes high
                if(rxf==1)
                begin
                    rd = 1;
                    oe = 1;
                    fifo_state=0;
                end else 
                begin
                    // check frame preamble bytes
                    if(preamble_state<3)
                    begin
                        wr_addr = 0;
                        if(preamble==data_in)
                            preamble_state=preamble_state+1;
                        else
                            preamble_state=0;
                    end else
                    if(preamble_state==3)
                    begin
                        // command byte (unused)
                        preamble_state=4;
                    end else
                    begin
                        // frame data bytes
                        wr_addr = wr_addr + 1;
                        // read in 2048 bytes (full frame)
                        if(wr_addr == 2048)
                        begin
                            wr_addr=0;
                            preamble_state = 0;
                            // swap to next buffer
                            buf_ready=!buf_ready;
                        end
                    end
                end
            end
    endcase
end

The fpga side of things a little bit more complex that you might need it as im checking the first three bytes in my packet to keep every thing in sync, if they are wrong it will discard the packet, you can chop this bit of code out if you want. It was for basic error checking and frame sync.

The above code is just the logic for reading in the bytes from the ftdi, give me a shout if you want the full source. It is sort of mixed in with the full project though hehe.