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Altera_Forum
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8 years ago

FSM Caught in impossible State

Hey all, So I've been developing an FPGA (Cyclone 3 Series) that basically sits between an FX3 USB 3 micro-controller and the HPI interface of a DSP. My problem lies withing my FSM, that is res...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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For some reason after I changed the signal that the wait_read_mult_done state was dependant on, the FSM now works. I guess the mult_done_sig only being high for 1 clock cycle wasn't long enough for the state machine to capture it?

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This would only be the case if the mult_done_sig was not synchronised properly into the same clock domain as the state machine, Or it failed timing (and you havent checked timing)