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Altera_Forum
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8 years ago

FSM Caught in impossible State

Hey all, So I've been developing an FPGA (Cyclone 3 Series) that basically sits between an FX3 USB 3 micro-controller and the HPI interface of a DSP. My problem lies withing my FSM, that is res...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Unfortunately I'm programming the FPGA through the FX3 using a Passive serial configuration so I don't have the jtag connection necessary for Signal Tap. I will try and do up a test bench for simulation purposes.

I have checked and all the inputs are indeed synced to the same clock, the state machine works fine under normal operation without the "wait_read_mult_done" state included.

Thanks for the reply's