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upsr's avatar
upsr
Icon for New Contributor rankNew Contributor
5 years ago

Frequency Sweep (Chirp) Generator

Hello,

I'm a complete newbie trying to implement a sweep (chirp) signal using the A10SoC dev kit and Analog Devices FMC-DAQ2 board. I was really hoping for some guidance of how to start implementing this.

The requirements of the frequency sweep is that it needs to sweep 5 Ghz (0-5) in under 50 us (The DAQ2 board cannot implment this requirement, however the project will be migrated to the AD9144 which can support this requirement). Unfortunately, I've not been able to find any kind of reference (paper, app note etc.) which can guide me in making this module. I've been trying to do this for a while but without any proper guidance (unfortunately) I'm completely lost as to what the architecture of the freq. generator module should be.

As far as progress is concerned, I've got the analog devices reference design (https://wiki.analog.com/resources/fpga/docs/hdl) running on the a10 development kit which implements a JESD204B communication protocol between the two boards. (https://wiki.analog.com/resources/eval/user-guides/ad-fmcdaq2-ebz/quickstart/a10soc)

In short, I need implement a frequency sweep generator which provides the samples as input to the transport layer of the JESD204B protocol. I'm really new to the world of FPGAs and unfortunately where I work I am the only person with any kind of FPGA experience, therefore, any kind of guidance, direction or even reference (paper, app note, anything) would be incredibly incredibly appreciated.

Any and all guidance would be really appreciated, thank you in advance!

Hope you have a wonderful day!

-U

1 Reply

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, you have some inquiries related to how to create a logic which could generate a chirp signal in the FPGA. This seems to be trending towards design implementation inquiry. For your information, generally in this Forum, we would be addressing specific inquiries related to FPGA ie device, IP but not design implementation. Sorry for the inconvenience. However, I will try our best to assist you to my best knowledge.


    For your information, as I search through the web, the following are some links which you may further look into to see if it is helpful. They seems to be using Matlab to achieve the chirp signal. Note that I am not a design specialist, thus could not really comment on the design implementation.


    https://www.mathworks.com/help/thingspeak/remove-dc-component-and-display-results.html


    https://www.matec-conferences.org/articles/matecconf/pdf/2017/42/matecconf_eitce2017_04009.pdf


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin