Frequency of StratixIV

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Uncomment the line "derive_pll_clocks -create_base_clocks" in pll.sdc and add in pll.sdc to your project through Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file. Let me know how this works.

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Hi protocol Enginner,

Finally it work, i bought license. And i try to calculate the time with alt_timestamp() function:).

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NO I meant in the RTL viewer. What you are seeing is only the top level view. To find the pll you will need to go down the hierarchy by looking inside the SOPC component. You can also try to find it in the tree (tree list on the left of the rtl view).

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Ah ok; think you very much Daixiwen.:)

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Yes, from what I see on the screenshots, you should be fine. If you want to find the pll that generates the 150MHz in the rtl viewer, you'll have to go deep into the sopc component.

If the code you want to test is too fast to get an accurate timing, you have two solutions:

[list]

[*]use a higher resolution timer instead of the system timer (it looks like you have a highres timer in your system)

[*]put your code in a big loop. As an example you can execute your code 1000 times, and then divide by 1000 the time you measured. Adjust the number of times you execute your code until you have the required accuracy.

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What do you mean go deep into the sopc component? Do you mean i change the option of the component. Think you for the solutions, for the second it's that i used.

Yes, from what I see on the screenshots, you should be fine. If you want to find the pll that generates the 150MHz in the rtl viewer, you'll have to go deep into the sopc component.

If the code you want to test is too fast to get an accurate timing, you have two solutions:[list][*]use a higher resolution timer instead of the system timer (it looks like you have a highres timer in your system)

[*]put your code in a big loop. As an example you can execute your code 1000 times, and then divide by 1000 the time you measured. Adjust the number of times you execute your code until you have the required accuracy.

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Your screenshots are extremely hard to read. From what I can decipher in the sopc shot, the CPU clock is 50MHz. Does it show 100MHz in the clock list when you change the setting in the pll component?

In the RTL view you should find the pll inside the sopc block, several levels down in the hierarchy.

You have lots of printf's in your code. This is typically an I/O operation than will take some time, even with a fast CPU. You should have a loop without any I/O between your two clock() calls if you really want to see a difference with a faster clock.

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Sorry for the quality of the screen. I attached the same screen in compressed folder.

How you after you decipher you say that the clock is 50 Mhz, if you see in the new screen, that the cpu clock is related to the sys_clk. And the sys_clk is an output from the pll.

Of course he show to me 150 Mhz in the clock list, you can check this from the screen of the SOPC. the PLL output also have as value 150Mhz.

In RTl schematic, i find just pll_125, this last don't related to clock CPU.

You have reason about the printf instruction, i note Daixiwen that i don't need for this. I add the printf instruction to see the result and to increase the execution time to appear the difference when i make some modifcation. You know that when i delete the printf instruction always i obtained 0 as execution time.

If there are a method to calculte the clock cycle or to appear the execution time in micro-second, really i will be happy to discover :).

Think you Daixiwen

Your screenshots are extremely hard to read. From what I can decipher in the sopc shot, the CPU clock is 50MHz. Does it show 100MHz in the clock list when you change the setting in the pll component?

In the RTL view you should find the pll inside the sopc block, several levels down in the hierarchy.

You have lots of printf's in your code. This is typically an I/O operation than will take some time, even with a fast CPU. You should have a loop without any I/O between your two clock() calls if you really want to see a difference with a faster clock.

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Could you show a screenshot of your sopc system? Are you sure the Nios CPU is using the correct clock? You should see the pll's output used as a clock in the RTL view.

How do you measure the execution time? What is the order of magnitude of the execution times you are measuring?

What does your loop do? Some actions (ex: i/o) will have an execution time that can be rather independant from the cpu clock.

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Of course in the joint file the screenshot of my SOPC system.

Of course as mentionned on the screen the NIos CPU is related to the correct clock.

I mentionned this in the back thread, i say that when i try to check in the RTL viewer, i find that clock isn't related to sys_clk(150mhz) from th pll, but it is is related directly to clkin_sys, when i go to check in the assignement menu i find that this pin is related to PIN_AC34. PIN_AC34 is related to an oscillator 50 Mhz as writen in the handbook of this kit.I add a screenschot of RTL to more explain for you.

For measurement time, i measure in the NIOS II software with the instruction clock().

I make exactly as this:

start =****();

my code ;

end= clock();

I put to your attention that tha instruction clock return tim in tick. I devise by 100 to abtained the execution time in second.

For me i need to puts the final in µsecond.

I add also my small program in the attached file. My loop will make some arithmetique operation (pow, add, multiplication) and every iteration there are a variable that give the decision to exit the loop or non. The maximum of iteration of the loop is 4.

I hope that is clear for you Daixiwen. If you need some information i wil be happy to more explain for you the problem.

Think you

Could you show a screenshot of your sopc system? Are you sure the Nios CPU is using the correct clock? You should see the pll's output used as a clock in the RTL view.

How do you measure the execution time? What is the order of magnitude of the execution times you are measuring?

What does your loop do? Some actions (ex: i/o) will have an execution time that can be rather independant from the cpu clock.

Hey protocol,

Yes you are understand my problem and think you very much for the explanation. my software he will contain only one loops.

Protocol, i constate a new thing that when i try to use the tools RTL View, in the schematic the cpu_clk is related directly to the sys_clk. In the assignement pins the sys_clk is related to PIN_AF34 (50 Mhz), i mean with this if the cpus_clk is always relted to sys_clk, it logic to give me always the same execution time.

Now, but in my SOPC i relate the cpu_clk to the pll.co (100Mhz). It is logic this or no?

Do you have any suggestion?