Frequency of StratixIV

Hey protocol,

Yes you are understand my problem and think you very much for the explanation. my software he will contain only one loops.

Protocol, i constate a new thing that when i try to use the tools RTL View, in the schematic the cpu_clk is related directly to the sys_clk. In the assignement pins the sys_clk is related to PIN_AF34 (50 Mhz), i mean with this if the cpus_clk is always relted to sys_clk, it logic to give me always the same execution time.

Now, but in my SOPC i relate the cpu_clk to the pll.co (100Mhz). It is logic this or no?

Do you have any suggestion?