Hi, Does anybody know where/how to find the operating frequency of a block ram? I particularly need M9K and M10K. I was not able to find them in the altera documentation. Kindly let me know if you have any info on this. Thanks.

AFAIK, it's not explicitly documented anywhere but with the exception of the M144K blocks you find on some devices, all the other blocks are usually capable of operating at the same frequency as the device's clock tree. Anyway, the best way is to synthesize a simple design and see what you can get.

Hi rbugalho, Thanks a lot for your reply. As far as synthesizing the design is concerned can you please tell me how to check for the frequency? When I specify the clock frequency to the M9K block say in a simple dual port mode using the Time Quest Analyser won't it operate at this frequency? Can you please let me know how to go about measuring the operating frequency?

I'm not sure if I'm understanding your question.. The RAM blocks will operate at frequency of the clock signal you use to drive them. You should specify that clock frequency in TimeQuest and TimeQuest will tell weather your design will operate (correctly) at that frequency or not. TimeQuest will also give you a (less reliable) estimate of the maximum frequency your design can operate at, in the fmax summary pane.

Hi rbugalho, I got what you are saying. I tried it. However I have a question.. I have synthesized a simple dual port ram having 32x8 depth and width. I use the TimeQuest Timing Analyser wizard to set the clock, input and output constraints. Setting the clock constraint is fine, but when I need to set the i/p and o/p constraints I need to select each of the 32 write data ports , 8 write and read address ports individually. Is there an easier way of doing this? Looking forward to your answer. Thanks.

--- Quote Start --- Setting the clock constraint is fine, but when I need to set the i/p and o/p constraints I need to select each of the 32 write data ports , 8 write and read address ports individually. Is there an easier way of doing this? --- Quote End --- To get valid timing results you have to use the RAM in the style you intend to use it. What you describe is an on-chip RAM instance that has its signals routed to I/O pins. This is probably not how you intend to use this RAM right? What you need to do is create a simplified design with a dual-port RAM instance in it. Then perform a TimeQuest analysis. To get the maximum performance from an on-chip RAM, you need to enable it to use its input and output registers, drive the input from registers, and capture the output to registers. You can then analyze the timing path from the input registers through the RAM to the output registers. I'll often create designs using a small Qsys system, eg., per this tutorial http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial and then either create the new component as a Qsys component, or create another component like your RAM that you can read or write to using say PIO. You can always cut the timing paths from the Qsys system to the input/output registers to isolate the path from TimeQuest analysis. Depending on how you do this, your design might not actually function correctly, but the timing results will be correct, i.e., TimeQuest will tell you what the delays are between the registers in the design. Note however that you're getting a little too focused on one aspect of the FPGA. Designs can not run on RAM alone. You're better off to come up with a simplified design and check the timing on that. Cheers, Dave

Frequency of operation of M9K bram | Altera Community

25 Replies

Altera_Forum
Honored Contributor
13 years ago
My guess would be that since 512 x 8-bits = 4kB, that the inference is dumb.

1024 x 8-bits = 8kB, which needs a whole M9K. Try that.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Dave, Jed.
_there's nothing wrong with inference of the memory module Jed has written_.

It's just that when instantiated within test_harness as top level module, the entire design gets reduced to 13 registers, of which the memory block takes only 8 bits. Quartus will not, by default, use a M9K RAM block for just 8 bits.

Inference of RAM blocks for Jed's 2W4R module is working correctly and when you surround it with some logic that actually makes use of 4096 bits, it will be inferred into RAM blocks.
Altera_Forum
Honored Contributor
13 years ago
Ok, I take back all the mean things I said about Quartus and its inference engine ... :)
Altera_Forum
Honored Contributor
13 years ago
The RAM is inferred when I connect the address ports too to the shift registers. Now everything is working fine.

rbugalho and Dave..Thanks a lot for helping me out.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Now everything is working fine.
--- Quote End ---

Wahoo! :)

Cheers,
Dave

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Frequency of operation of M9K bram

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