Forum Discussion
Altera_Forum
Honored Contributor
11 years agoFirsly look at the post snythesis netlist (technology map viewer). Most likely the inverters have been discarded during synthesis. Read about the "synthesis keep" attributes that have to be applied. There are several previous forum threads about generating logic cell delay.
Your expectations about the delay are probably wrong. I would calculate about 0.25 ns per LE with MAX II or Cyclone series.