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Altera_Forum's avatar
Altera_Forum
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18 years ago

Frequency divider with clk en.

I want to make a frequency divider (50 Mhz to any value, 560khz ), I am working with a counter like a freq. divider but there is a warning in Quartus II:

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

I read that using a CLK EN is the best way to make a freq. divider, but a I don't know nothing about it, DO YOU HAVE INFORMATION OR EXAMPLES ABOUT? HELP ME PLEASE

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  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Now, I'm considering a PLL like freq divider, Do you have information about it ? (I'm using DE1 board).

    Thanks vernmid.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    It sounds like you're using the output of a register in your divider to act as a clock, hence the warning.

    The clock enable method means that, for example, to generate your (approx.) 560kHz clock, you should actually generate a clock enable signal which goes high for one clock cycle in every 89. You then use this signal along with the original 50Mhz clock to drive whatever logic needs the slower clock. You then just have to make sure that this logic only responds to clock edges when clock enable is high. In Verilog it would be something like this:

    always @ (posedge clk)

    begin

    if(clk_en)

    // Do whatever
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Could you post a code fragment of your counter. It would really help with solving your problem.

    Have you considered using a PLL for your frequency divider?

    Rgds