Frequency Counter in Verilog?

You failed to mention whether this module will be synthesized or if it is only for simulation. If it is for synthesis, it will not compile as your are breaking a few rules. In either case, give this a try. I didn't compile this but you get the idea

module f_count(
    input               resetn,
    input               ref_clock,
    input               in_clock,
    output  reg   f_measurment
);
reg        in_clock_rsync;
wire            in_clock_rise;
reg       count;
// Look for rising edge of in_clock
assign  in_clock_rise = ~in_clock_rsync & in_clock_rsync;
// Resynchronize in_clock to ref_clock domain
always @(posedge ref_clock)
                    in_clock_rsync  <= {in_clock_rsync,in_clock};
always @(posedge ref_clock or negedge resetn)
    if(!resetn) begin
                    count           <= 14'd0;           // reset counter
                    f_measurment    <= 14'd0;           // reset output
    end else begin
                    count           <= count + 14'd1;   // increment counter by default
        if(in_clock_rise) begin
                    count           <= 14'd0;           // reset counter
                    f_measurment    <= 10000 / count;   // determine output
        end
    end
endmodule

Your 10khz reference clock obviously doesn't allow you to measure a wide range of frequencies. You can really only measure frequencies between 1Hz and 5kHz and of course at higher frequencies, you'll have more error.

Jake