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Altera_Forum's avatar
Altera_Forum
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9 years ago

freeze root of all design after every change in it

Hi, I am implementing a communication system on the 114 k logic cyclone IV FPGA using Quartus 11.1 and My design use 80% of the chip. adding or removing every block to design can result to destroy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

You need to check that your design meets timing. In it's simplest form - have you constrained all your clocks? (Have you told Quartus the frequency of each clock?)

After compilation, check the timing reports. Does it meet timing? If there is a problem with tsu your design would not run fast enough.

Cheers,

Alex