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Altera_Forum's avatar
Altera_Forum
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9 years ago

freeze root of all design after every change in it

Hi, I am implementing a communication system on the 114 k logic cyclone IV FPGA using Quartus 11.1 and My design use 80% of the chip. adding or removing every block to design can result to destroy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Unfortunately, using a relatively large device that is very full is going to be time consuming...

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use tsu and thold to over come these bad complition?

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I'm not sure what you mean by this. These are not parameters you can adjust. A poor design may not meet the tsu required for it to operate at a particular clock frequency. So, it will fail timing. If this is the case you need to look at your code.

Cheers,

Alex