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Altera_Forum
Honored Contributor
Honored Contributorfreeze root of all design after every change in it
Hi, I am implementing a communication system on the 114 k logic cyclone IV FPGA using Quartus 11.1 and My design use 80% of the chip. adding or removing every block to design can result to destroy...
Altera_ForumHonored Contributor
Honored ContributorHi,
Many Thanks. Changing these settings is time consuming. Because the time of complition increased a lot. Are you use tsu and thold to over come these bad complition? Offcurse this bad rooting can be occured in the state 40 % of chip using.
