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Altera_Forum's avatar
Altera_Forum
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9 years ago

freeze root of all design after every change in it

Hi, I am implementing a communication system on the 114 k logic cyclone IV FPGA using Quartus 11.1 and My design use 80% of the chip. adding or removing every block to design can result to destroy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Fitting 'a little bit' more into a very full device can be very difficult. It may use 80% of the resources but how much of the routing has been used is not shown. Locking the part of the design you already have is not likely to help.

You can try increasing the effort Quartus puts in to fitting your design. Under 'Assignments' -> 'Settings...', select the 'Compiler Settings' Category. Click 'Advanced Settings (Fitter)...'. Try changing the 'ALM Register Packing Effort' to 'High'. You can also play with the 'Auto Packed Registers' setting. Finally, the 'Fitter Initial Placement Seed' and 'Placement Effort Multiplier' will also yield different results, which may help realise a fit.

Cheers,

Alex