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I have a hard time imagining how you could use some simple analog off chip circuitry to raise the frequency of your clock from 50 Hz to 5MHz in order to use the PLL. I guess that you could have a succession of selective filters that would work on harmonics but I wouldn't call that solution simple, elegant, or low noise/jitter, if it can even work in the first place.
If you already have a solution with an external chip that works well maybe you should keep it.
It may be a stupid question but why do you need that in the first place? Couldn't you use a normal crystal oscillator and use logic to synchronize to the 50 Hz input instead? Do you really need that clock to be exactly 10^6 times the frequency of the input clock?
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Thanks, Daixiwen. I'm sure you're right about just using the chip solution i have. Creating a soft IP version of the chip for FPGA is not my first task. Just something that occurred to me.
Yes, i need to sync 10^6 for my application. I'm interested in your idea - use a normal crystal oscillator and use logic to synchronize. It sounds hopeful, but i'm not sure it will work for my application - can you elaborate or point me to a reference? I'm interested in all ideas. Thanks for your help.
I need locked at the 10^6 input, but absolute phase not necessary - for every single cycle at 50Hz. i need 50M evenly spaced cycles. Phase locked also acceptable.
Cheers,
Honored Contributor
