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Would it be possible to clarify this with the design team, perhaps?
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You can always try putting a basic FPGA design together to prove you can realise a fit when using these pins as bi-directional pins in user mode. I don't see you having any trouble with that.
Thinking about the case where you host external memory from these FPGA pins - the scenario the documentation suggests isn't supported - this sounds somewhat compromised anyway. You boot your FPGA from this external memory device and then give your FPGA direct access to it, potentially allowing you to overwrite your boot image. Yes - disciplined operation could avoid that. However, if this was deliberate - allowing you to upgrade the FPGA's boot image - and something failed (e.g. power), then you render your system useless. I can't see that this
is the reason for this limitation but it's an issue worth avoiding.
Cheers,
Alex
Honored Contributor
