fPLL to IOPLL cascading | Stratix 10

I am working on a design in which I'd like to receive transceiver data synchronous to an fPLL clock, and then transfer that data to another part of a design using a collection of synchronous I/O PLL generated clocks. Is there any guidance or documentation for cascading an fPLL clock to an I/O PLL such that the fPLL output clock (I/O PLL reference clock) is phase aligned/synchronous to the I/O PLL output clocks?

Thanks!