fPLL loose lock debug help request

Hello,

I am using Arria 10 GX FPGA Development board.

I am debugging a fPLL lock issue.

In current design fPLL instance gets reference clock from the recovered clock of transceiver.

CDR block of transceiver is configured for manual mode.

Currently I am manually setting CDR block to LTR mode. I do see expected and stable recovered clock.

But unable to get fPLL locked to this recovered clock.

Any help as to debug will be really helpful.

Thanks & Regards,

Sachin Jadhav