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I figure I can pull nCONFIG low and then pull high to force (essentially) an FPGA reset using an external IC. But, has anyone heard of such a thing being done?
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Yes, I do this. You can consider this a function of the external programmer, i.e., if you want to clear the current configuration, you just pulse configN low.
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I would think that FPGA's wouldn't "lock-up", and that this whole thing may introduce new issues, i.e. during power-up.
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FPGAs don't really lock-up, though there is the non-zero chance that an SRAM-based FPGA can have its configuration corrupted, eg., due to cosmic rays in a space-borne application (where you did not use a rad-hard FPGA).
In general your FPGA watchdog will be there to protect you from a critical state machine (with a coding error) that can get 'stuck'.
For example, consider the case of a processor with an FPGA on its external bus. When the processor does a read, the FPGA uses a handshake to accept the read, and then inserts wait-states until the read-data is valid. So what happens if the read-data is never valid ... the processor is locked up.
In this case though, the lockup would be cleared by an FPGA
reset, rather than complete reconfiguration.
So you need to decide what kind of lock-up you are trying to protect against. I suspect you need a watchdog that will reset the FPGA, not force reconfiguration (or you could implement two watchdogs).
Cheers,
Dave
Honored Contributor
