fpga triststate

To understand the restrictions in synthesis of internal tristate nodes, it's important to know, that CPLD, FPGA or ASIC have no real internal tristate capability, only unidirectional point-to-point connections between logic cells.

Thus an internal tristate construct has always to be translated to multiplexers. In a real tristate circuit, multiple drivers can drive out simultaneously (although causing a bus contention). This can't happen in multiplexer circuits, all concurrent enable signals for a particular tristate node must be combined to an unequivocal multiplexer select signal.

Internal tristate conflicts respectively synthesis failure ususally happens, if no clear multiplexer select condition can be found. This may be the case, cause the select conditions are actually conflicting or at least unknown in part. You have to change the design to remove the problem. As a simple rule, all select conditions should be derived by asynchronous logic from the same signal set in an exclusive way.

The other option would be to use multiplexers instead of tristate nodes explicitely in your design.