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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPGA-to-HPS SDRAM Interface blocks whole HPS

Hello,

I have configured in QSYS f2h_sdram0 as Avalon-MM Bidirectional with a width of 64 bits.

Whatever I connect to this interface, blocks the HPS when I run "run bridge_enable_handoff" in the uboot console.

( Tried the SGDMA which freezes instantly, the NIOS II core which freezes upon a RAM access... )

Preloader and uboot are of course regenerated each time I change the design.

What can be the reason of this behaviour? Misconfiguration of pin assignments to the RAM in Quartus?

But Linux seems to work on the HPS.

Thanks

Hannes

Edit: With security enabled at least no freeze with the SGDMA.

Edit2: If I forgot to mention something important, please tell me.

When frozen, everything on the f2h_sdram0 is set to 0 (data address, data_burstcount, data_byteenable, data_writedata, data_readdata)

Is this important? Is there anything I can test using Signaltap?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hey! Now works fine for me too :).

    But i really don't understand why we need to do that.

    Anyone knows???

    Is that the "device tree" can help ?

    Nico
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I wonder if it would also work if the FPGA was configured from Linux. You would need to wait for configuration to finish, enable the FPGA-to-HPS SDRAM bridge, and only then make an access from the FPGA.