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Altera_Forum's avatar
Altera_Forum
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10 years ago

FPGA to HPS interrupts

Hi,

I'm trying to interrupt HPS from FPGA. I'm generating interrupts from the slave on the FPGA which I can see it on the signal tap. I'm checking for interrupts in Linux using 'cat /proc/interrupts', I see that my interrupts are registered but I don't get any interrupts.

In the RTL viewer (shown in fig 1; HPS.jpg), I see that the interrupt bus (f2h_irq_p0[31:0] & f2h_irq_p1[31:0]) are not connected to anything in the 'fpga to hps interfaces'( this is the block where it shows connections of all the bridges between HPS and FPGA). Is it just not illustrated in the RTL viewer or is not connected.

I don't know what I'm doing wrong or if I'm missing something. Do I have to make any changes to the device tree? Or should I enable something like I enable the bridges?

Thanks,

Karthik

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    That connection to nowhere is a red herring, it really is connected. The reason why some of those other ports connect to blocks is for other reasons which would take too long to explain (and you don't need to care :))

    One thing to be aware of is that those 64 interrupts from the FPGA can be level or edge sensitive so I would make sure the interrupt setting matches what your hardware provides, for example if your hardware provides an interrupt pulse but the GIC in the HPS is setup for level sensitive interrupts then the interrupt will be missed.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks for reply!

    After reading your comment I increased the width of my interrupt and surely HPS is catching the interrupts now. So, I can conclude GIC in the HPS is setup to be level sensitive and was missing my interrupts edge. I didn't find any documentation on how to setup GIC to be level or edge sensitive. Could you please tell me how to do this or give me a link where this is discussed.

    Thanks,

    Karthik.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If the GIC was setup for level sensitive interrupts I would expect the code that checks for spurious interrupts would have filtered it out. Unfortunately I'm a hardware engineer so I don't know what to point you at but if you look at the code used by some of the other peripherals in the HPS that use edge sensitive interrupts that might be a good starting point.

    By increasing the width of the pulse fixing the issue I suspect the pulse width was too narrow for the edge detector to capture it. Typically edge detectors need a two cycle (or more) pulse width. I think the edge detection occurs after the clock crossing so it would be on the 1/4th MPU clock frequency so I would make sure your pulse width is larger than two MPU clock cycles to ensure it always gets captured. So the GIC might be defaulting to edge sensitive and the problem was the pulse was just being lost. If you had a single cycle pulse and only increased it by a couple of clock cycles then the GIC is probably using edge sensitive interrupts but if you increased the pulse width a lot then it's probably setup for level sensitive.